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| a FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 8-Bit Resolution Linearity: 1/4 LSB DNL Linearity: 1/4 LSB INL Differential Current Outputs SINAD @ 5 MHz Output: 50 dB Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V Power-Down Mode: 20 mW @ 5 V On-Chip 1.20 V Reference Single +5 V or +3 V Supply Operation Packages: 28-Lead SOIC and 28-Lead TSSOP Edge-Triggered Latches Fast Settling: 35 ns Full-Scale Settling to 0.1% APPLICATIONS Communications Signal Reconstruction Instrumentation PRODUCT DESCRIPTION 8-Bit, 100 MSPS+ TxDAC(R) D/A Converter AD9708* FUNCTIONAL BLOCK DIAGRAM +5V 0.1 F REFLO +1.20V REF 0.1 F REF IO FS ADJ RSET +5V DVDD DCOM CLOCK SLEEP COMP1 AVDD ACOM 50pF CURRENT SOURCE ARRAY SEGMENTED SWITCHES LATCHES AD9708 COMP2 0.1 F IOUTA IOUTB CLOCK DIGITAL DATA INPUTS (DB7-DB0) Differential current outputs are provided to support singleended or differential applications. The current outputs may be directly tied to an output resistor to provide two complementary, single-ended voltage outputs. The output voltage compliance range is 1.25 V. The AD9708 contains a 1.2 V on-chip reference and reference control amplifier, which allows the full-scale output current to be simply set by a single resistor. The AD9708 can be driven by a variety of external reference voltages. The AD9708's full-scale current can be adjusted over a 2 mA to 20 mA range without any degradation in dynamic performance. Thus, the AD9708 may operate at reduced power levels or be adjusted over a 20 dB range to provide additional gain ranging capabilities. The AD9708 is available in 28-lead SOIC and 28-lead TSSOP packages. It is specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS The AD9708 is the 8-bit resolution member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, was specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. The AD9708 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS. The AD9708's flexible single-supply operating range of +2.7 V to +5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further reduced to 45 mW, without a significant degradation in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 20 mW. The AD9708 is manufactured on an advanced CMOS process. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a temperature compensated bandgap reference have been integrated to provide a complete monolithic DAC solution. Flexible supply options support +3 V and +5 V CMOS logic families. The AD9708 is a current-output DAC with a nominal full-scale output current of 20 mA and > 100 k output impedance. TxDAC is a registered trademark of Analog Devices, Inc. *Patent pending. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 1. The AD9708 is a member of the TxDAC product family, which provides an upward or downward component selection path based on resolution (8 to 14 bits), performance and cost. 2. Manufactured on a CMOS process, the AD9708 uses a proprietary switching technique that enhances dynamic performance well beyond 8- and 10-bit video DACs. 3. On-chip, edge-triggered input CMOS latches readily interface to +3 V and +5 V CMOS logic families. The AD9708 can support update rates up to 125 MSPS. 4. A flexible single-supply operating range of +2.7 V to +5.5 V and a wide full-scale current adjustment span of 2 mA to 20 mA allows the AD9708 to operate at reduced power levels (i.e., 45 mW) without any degradation in dynamic performance. 5. A temperature compensated, 1.20 V bandgap reference is included on-chip providing a complete DAC solution. An external reference may be used. 6. The current output(s) of the AD9708 can easily be configured for various single-ended or differential applications. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD9708-SPECIFICATIONS DC SPECIFICATIONS (T Parameter RESOLUTION MONOTONICITY DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth (w/o CCOMP1)4 TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD5 DVDD Analog Supply Current (IAVDD ) Digital Supply Current (IDVDD)6 Supply Current Sleep Mode (IAVDD) Power Dissipation6 (5 V, IOUTFS = 20 mA) Power Dissipation7 (5 V, IOUTFS = 20 mA) Power Dissipation7 (3 V, IOUTFS = 2 mA) Power Supply Rejection Ratio--AVDD Power Supply Rejection Ratio--DVDD OPERATING RANGE 1 MIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted) Min 8 Typ Max Units Bits GUARANTEED OVER SPECIFIED TEMPERATURE RANGE -1/2 -1/2 -0.025 -10 -10 2.0 -1.0 1/4 1/4 +1/2 +1/2 +0.025 +10 +10 20.0 1.25 LSB LSB % of FSR % of FSR % of FSR mA V k pF V nA V M MHz ppm of FSR/C ppm of FSR/C ppm of FSR/C ppm/C 2 1 100 5 1.08 1.20 100 1.32 0.1 1 1.4 0 50 100 50 1.25 2.7 2.7 5.0 5.0 25 3 140 190 45 5.5 5.5 30 6 8.5 175 -0.4 -0.025 -40 +0.4 +0.025 +85 V V mA mA mA mW mW mW % of FSR/V % of FSR/V C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 x the I REF current. 3 Use an external buffer amplifier to drive any external load. 4 Reference bandwidth is a function of external cap at COMP1 pin. 5 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6 Measured at fCLOCK = 50 MSPS and fOUT = 1.0 MHz. 7 Measured as unbuffered voltage output into 50 RLOAD at IOUTA and IOUTB, f CLOCK = 100 MSPS and fOUT = 40 MHz. Specifications subject to change without notice. -2- REV. B AD9708 DYNAMIC SPECIFICATIONS Terminated, unless otherwise noted) Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST ) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (I OUTFS = 20 mA) Output Noise (I OUTFS = 2 mA) AC LINEARITY TO NYQUIST Signal-to-Noise and Distortion Ratio fCLOCK = 10 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 12.51 MHz fCLOCK = 100 MSPS; fOUT = 5.01 MHz fCLOCK = 100 MSPS; fOUT = 25.01 MHz Total Harmonic Distortion fCLOCK = 10 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 12.51 MHz fCLOCK = 100 MSPS; fOUT = 5.01 MHz fCLOCK = 100 MSPS; fOUT = 25.01 MHz Spurious-Free Dynamic Range to Nyquist fCLOCK = 10 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 12.51 MHz fCLOCK = 100 MSPS; fOUT = 5.01 MHz fCLOCK = 100 MSPS; fOUT = 25.01 MHz NOTES 1 Measured single ended into 50 load. Specifications subject to change without notice. (TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Single-Ended Output, IOUTA, 50 Min 100 Typ 125 35 1 5 2.5 2.5 50 30 Max Doubly Units MSPS ns ns pV-s ns ns pA/Hz pA/Hz 50 50 48 50 45 -67 -67 -59 -64 -48 62 68 68 63 67 50 -62 dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc DIGITAL SPECIFICATIONS (T Parameter DIGITAL INPUTS Logic "1" Voltage @ DVDD = +5 V Logic "1" Voltage @ DVDD = +3 V Logic "0" Voltage @ DVDD = +5 V Logic "0" Voltage @ DVDD = +3 V Logic "1" Current Logic "0" Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (t LPW) Specifications subject to change without notice. MIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted) Min 3.5 2.1 -10 -10 5 2.0 1.5 Typ 5 3 0 0 Max Units V V V V A A pF ns ns 1.3 0.9 +10 +10 3.5 ns DB0-DB7 tS CLOCK tH tLPW tPD tST 0.1% 0.1% IOUTA OR IOUTB Figure 1. Timing Diagram REV. B -3- AD9708 ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DVDD ACOM AVDD CLOCK, SLEEP Digital Inputs IOUTA, IOUTB COMP1, COMP2 REFIO, FSADJ REFLO Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to ACOM DCOM DCOM DVDD DCOM DCOM ACOM ACOM ACOM ACOM Min -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -1.0 -0.3 -0.3 -0.3 -65 Max +6.5 +6.5 +0.3 +6.5 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +0.3 +150 +150 +300 Units V V V V V V V V V V C C C PIN FUNCTION DESCRIPTIONS Pin No. Name 1 2-7 8 9-14, 25 15 DB7 DB6-DB1 DB0 NC SLEEP Description Most Significant Data Bit (MSB). Data Bits 1-6. Least Significant Data Bit (LSB). No Internal Connection. Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1 F capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. Bandwidth/Noise Reduction Node. Add 0.1 F to AVDD for optimum performance. Analog Common. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 F capacitor. Analog Supply Voltage (+2.7 V to +5.5 V). Digital Common. Digital Supply Voltage (+2.7 V to +5.5 V). Clock Input. Data latched on positive edge of clock. 16 REFLO 17 REFIO *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 18 19 FS ADJ COMP1 28-Lead 300 mil SOIC JA = 71.4C/W JC = 23C/W 28-Lead TSSOP JA = 97.9C/W JC = 14.0C/W PIN CONFIGURATION 28 CLOCK 27 DVDD 26 DCOM 25 NC 20 21 ACOM IOUTB 22 23 IOUTA COMP2 (MSB) DB7 1 DB6 2 DB5 3 DB4 4 DB3 5 DB2 6 24 26 27 28 AVDD DCOM DVDD CLOCK AD9708 24 AVDD TOP VIEW 23 COMP2 DB1 7 (Not to Scale) 22 IOUTA 21 IOUTB 20 ACOM 19 COMP1 18 FS ADJ 17 REFIO 16 REFLO 15 SLEEP DB0 8 NC 9 NC 10 NC 11 NC 12 NC 13 NC 14 ORDERING GUIDE Temperature Range Package Descriptions Package Options* Model NC = NO CONNECT AD9708AR -40C to +85C 28-Lead 300 Mil SOIC R-28 AD9708ARU -40C to +85C 28-Lead TSSOP RU-28 AD9708-EB Evaluation Board *R = Small Outline IC; RU = Thin Small Outline IC. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9708 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. B AD9708 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (or DNL) offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. Power Supply Rejection DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Spurious-Free Dynamic Range The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Output Compliance Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. Temperature Drift S/N+D is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Total Harmonic Distortion Temperature drift is specified as the maximum change from the ambient (+25C) value to the value at either TMIN or TMAX . For +5V 0.1 F THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured output signal. It is expressed as a percentage or in decibels (dB). REFLO +1.20V REF 0.1 F REF IO FS ADJ RSET 2k +5V DVDD DCOM CLOCK DVDD DCOM RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR COMP1 50pF AVDD ACOM AD9708 CURRENT SOURCE ARRAY COMP2 0.1 F IOUTA SEGMENTED SWITCHES LATCHES IOUTB 50 20pF 50 SLEEP 50 CLOCK OUTPUT DIGITAL DATA TEKTRONIX AWG-2021 20pF TO HP3589A SPECTRUM/ NETWORK ANALYZER 50 INPUT * AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. Figure 2. Basic AC Characterization Test Setup REV. B -5- AD9708 Typical AC Characterization Curves (AVDD = +5 V or +3 V, DVDD = +5 V or +3 V, 50 Single-Ended Output, IOUTA, IOUTFS = 20 mA, TA = +25 C, unless otherwise noted) 70 THD @ 50MSPS 65 SINAD/THD - dB 60 55 50 45 40 0.1 THD @ 10MSPS THD @ 100MSPS SINAD/THD - dB 65 THD @ 100MSPS 60 SINAD - dB 45 THD @ 50MSPS 55 50 45 40 0.1 70 THD @ 10MSPS 55 Doubly Terminated Load, IOUTFS = 20mA 50 IOUTFS = 10mA IOUTFS = 5mA 40 IOUTFS = 2.5mA SINAD @ 10MSPS SINAD @ 50MSPS SINAD @ 100MSPS 10 1 FREQUENCY - MHz 100 SINAD @ 10MSPS SINAD @ 50MSPS SINAD @ 100MSPS 10 1 FREQUENCY - MHz 100 30 1 10 FREQUENCY - MHz 100 35 Figure 3. SINAD/THD vs. fOUT (AVDD and DVDD = 5.0 V) Figure 4. SINAD/THD vs. f OUT (Differential Output, AVDD and DVDD = 5.0 V) Figure 5. SINAD vs. IOUTFS @ 100 MSPS 70 65 THD @ 10MSPS SINAD/THD - dB 60 THD @ 50MSPS 55 50 45 40 0.1 70 65 SINAD/THD - dB 60 SINAD - dB THD @ 10MSPS THD @ 50MSPS 52 IOUTFS = 20mA 50 IOUTFS = 10mA IOUTFS = 5mA 48 IOUTFS = 2.5mA THD @ 100MSPS 55 THD @ 100MSPS 50 45 SINAD @ 100MSPS 40 0.1 SINAD @ 10MSPS SINAD @ 50MSPS 46 SINAD @ 10MSPS SINAD @ 50MSPS SINAD @ 100MSPS 1 10 FREQUENCY - MHz 100 44 1 10 FREQUENCY - MHz 100 42 0.1 1 FREQUENCY - MHz 10 Figure 6. SINAD/THD vs. fOUT (AVDD and DVDD = 3.0 V) Figure 7. SINAD/THD vs. f OUT (Differential Output, AVDD and DVDD = 3.0 V) Figure 8. SINAD vs. IOUTFS @ 20 MSPS 0 fCLOCK = 25MSPS fOUT = 7.81MHz SFDR = +60.7dBc AMPLITUDE = 0dBFS 10dB - Div 10dB - Div 0 fCLOCK = 125MSPS fOUT = 27.0MHz SFDR = +52.7dBc AMPLITUDE = 0dBc 0.6 0.5 0.4 0.3 VOLTS START: 0Hz STOP: 62.5MHz 0.2 0.1 0.0 -0.1 -100 START: 0Hz STOP: 12.5MHz -100 -0.2 TIME - 5ns/Div Figure 9. Single-Tone Spectral Plot @ 25 MSPS Figure 10. Single-Tone Spectral Plot @ 125 MSPS Figure 11. Step Response -6- REV. B AD9708 FUNCTIONAL DESCRIPTION Figure 12 shows a simplified block diagram of the AD9708. The AD9708 consists of a large PMOS current source array capable of providing up to 20 mA of total current. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The remaining 3 LSBs are also implemented with equally weighted current sources whose sum total equals 7/8th of an MSB current source. Implementing the upper and lower bits with current sources helps maintain the DAC's high output impedance (i.e. > 100 k). All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. The analog and digital sections of the AD9708 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 2.7 volt to 5.5 volt range. The digital section, which is capable of operating up to a 125 MSPS clock rate, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.20 V bandgap voltage reference and a reference control amplifier. The full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET. The external resistor, in combination with both the reference control amplifier and voltage reference VREFIO, sets the reference current I REF, which is mirrored over to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is thirty-two times the value of IREF. DAC TRANSFER FUNCTION As previously mentioned, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage VREFIO and external resistor RSET. It can be expressed as: IOUTFS = 32 x IREF where IREF = VREFIO /RSET (4) The two current outputs will typically drive a resistive load directly. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, which are tied to analog common, ACOM. Note, RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 or 75 cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply: VOUTA = IOUTA x R LOAD V OUTB = IOUTB x R LOAD (5) (6) (3) Note the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. The differential voltage, VDIFF , appearing across IOUTA and IOUTB is: VDIFF = (IOUTA - IOUTB) x RLOAD (7) Substituting the values of IOUTA , IOUTB, and IREF; VDIFF can be expressed as: VDIFF = {(2 DAC CODE - 255)/256}/ x (32 RLOAD /RSET) x VREFIO VOLTAGE REFERENCE AND CONTROL AMPLIFIER (8) The AD9708 provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 255), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB are a function of both the input code and IOUTFS and can be expressed as: IOUTA = (DAC CODE/256) x IOUTFS IOUTB = (255 - DAC CODE)/256 x IOUTFS (1) (2) where DAC CODE = 0 to 255 (i.e., Decimal Representation). The AD9708 contains an internal 1.20 V bandgap reference that can be easily disabled and overridden by an external reference. REFIO serves as either an input or output depending on whether the internal or an external reference is selected. If REFLO is tied to ACOM, as shown in Figure 13, the internal reference is activated and REFIO provides a 1.20 V output. In this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 F or greater from REFIO to REFLO. Note that REFIO is not designed to drive any external load. It should be buffered with an external amplifier having an input bias current less than 100 nA if any additional loading is required. +5V 0.1 F REFLO +1.20V REF VREFIO 0.1 F RSET 2k IREF REFIO FS ADJ COMP1 50pF AVDD ACOM AD9708 CURRENT SOURCE ARRAY COMP2 0.1 F VDIFF = VOUTA - VOUTB +5V DVDD DCOM SEGMENTED SWITCHES LATCHES SLEEP DIGITAL DATA INPUTS (DB7-DB0) IOUTA IOUTB IOUTA IOUTB VOUTB RLOAD 50 VOUTA RLOAD 50 CLOCK CLOCK Figure 12. Functional Block Diagram REV. B -7- AD9708 +5V 0.1 F OPTIONAL EXTERNAL REF BUFFER REFLO +1.2V REF REFIO 50pF COMP1 AVDD ADDITIONAL LOAD 0.1 F 2k FS ADJ CURRENT SOURCE ARRAY AD9708 The small signal bandwidth of the reference control amplifier is approximately 1.8 MHz and can be reduced by connecting an external capacitor between COMP1 and AVDD. The output of the control amplifier, COMP1, is internally compensated via a 50 pF capacitor that limits the control amplifier small-signal bandwidth and reduces its output impedance. Any additional external capacitance further limits the bandwidth and acts as a filter to reduce the noise contribution from the reference amplifier. If IREF is fixed for an application, a 0.1 F ceramic chip capacitor is recommended. IREF can be varied for a fixed RSET by disabling the internal reference and varying the common-mode voltage over its compliance range of 1.25 V to 0.10 V. REFIO can be driven by a single-supply amplifier or DAC, thus allowing IREF to be varied for a fixed RSET. Since the input impedance of REFIO is approximately 1 M, a simple R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown in Figure 15 using the AD7524 and an external 1.2 V reference, the AD1580. Note another AD9708 could also be used as the gain control DAC since it can also provide a programmable unipolar output up to 1.2 V. ANALOG OUTPUTS AND OUTPUT CONFIGURATIONS Figure 13. Internal Reference Configuration The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external reference may then be applied to REFIO as shown in Figure 14. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 F compensation capacitor is not required since the internal reference is disabled, and the high input impedance (i.e., 1 M) of REFIO minimizes any loading of the external reference. AVDD 0.1 F AVDD VREFIO REFLO +1.2V REF 50pF REFIO FS ADJ RSET IREF = VREFIO/RSET COMP1 AVDD EXTERNAL REF CURRENT SOURCE ARRAY REFERENCE CONTROL AMPLIFIER AD9708 Figure 14. External Reference Configuration The AD9708 also contains an internal control amplifier that is used to regulate the DAC's full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 14, such that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 A and 625 A. The wide adjustment span of IOUTFS provides several application benefits. The first benefit relates directly to the power dissipation of the AD9708, which is proportional to IOUTFS (refer to the POWER DISSIPATION section). The second benefit relates to the 20 dB adjustment, which is useful for system gain control purposes. The AD9708 produces two complementary current outputs, IOUTA and IOUTB , which may be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC TRANSFER FUNCTION section. Figure 16 shows the AD9708 configured to provide a positive unipolar output range of approximately 0 V to +0.5 V for a double terminated 50 cable for a nominal full-scale current, IOUTFS, of 20 mA. In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB and is equal to 25 . The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. AD9708 IOUTA 22 50 IOUTB 21 25 IOUTFS = 20mA VOUTA = 0 TO +0.5V 50 Figure 16. 0 V to +0.5 V Unbuffered Voltage Output Alternatively, an amplifier could be configured as an I-V converter thus converting IOUTA or IOUTB into a negative unipolar AVDD OPTIONAL BANDLIMITING CAPACITOR REFLO COMP1 50pF CURRENT SOURCE ARRAY AVDD AVDD RFB 1.2V OUT1 OUT2 AGND VDD VREF 0.1V TO 1.2V +1.2V REF REFIO FS ADJ RSET IREF = VREF/RSET AD7524 AD1580 AD9708 DB7-DB0 Figure 15. Single-Supply Gain Control Circuit -8- REV. B AD9708 voltage. Figure 17 shows a buffered singled-ended output configuration in which the op amp, U1, performs an I-V conversion on the AD9708 output current. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1's voltage output swing capabilities by scaling IOUTFS and/or RFB . An improvement in ac distortion performance may result with a reduced IOUTFS, since the signal current U1 will be required to sink and will be subsequently reduced. Note, the ac distortion performance of this circuit at higher DAC update rates may be limited by U1's slewing capabilities. COPT RFB 200 over a digital supply range of 2.7 V to 5.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage, VOH(MAX) , of the TTL drivers. A DVDD of 3 V to 3.3 V will typically ensure upper compatibility of most TTL logic families. DVDD DIGITAL INPUT Figure 18. Equivalent Digital Input AD9708 IOUTA 22 IOUTFS = 10mA U1 IOUTB 21 200 VOUT = IOUTFS RFB Figure 17. Unipolar Buffered Voltage Output IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA. Applications requiring the AD9708's output (i.e., VOUTA and/or VOUTB) to extend up to its output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely affect the AD9708's linearity. The differential voltage, VDIFF , existing between VOUTA and VOUTB may also be converted to a single-ended voltage via a transformer or differential amplifier configuration. Refer to the DIFFERENTIAL OUTPUT CONFIGURATION section for more information. DIGITAL INPUTS Since the AD9708 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum setup-and-hold times of the AD9708 as well as its required min/ max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise. Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion of a low value resistor network (i.e., 20 to 100 ) between the AD9708 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. For longer run lengths and high data update rates, strip line techniques with proper termination resistors should be considered to maintain "clean" digital inputs. Also, operating the AD9708 with reduced logic swings and a corresponding digital supply (DVDD) will also reduce data feedthrough. The external clock driver circuitry should provide the AD9708 with a low jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform. However, the clock input could also be driven by via a sine wave, which is centered around the digital threshold (i.e., DVDD/2), and meets the min/max logic threshold. This may result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. Note, at higher sampling rates the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and subsequently cut into the required data setup-and-hold times. SLEEP MODE OPERATION The AD9708's digital input consists of eight data input pins and a clock input pin. The 8-bit parallel data inputs follow standard positive binary coding where DB7 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). The digital interface is implemented using an edge-triggered master slave latch. The DAC output is updated following the rising edge of the clock as shown in Figure 1 and is designed to support a clock rate as high as 125 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth. The setup-and-hold times can also be varied within the clock cycle as long as the specified minimum times are met; although the location of these transition edges may affect digital feedthrough and distortion performance. The digital inputs are CMOS compatible with logic thresholds, VTHRESHOLD set to approximately half the digital positive supply (DVDD) or VTHRESHOLD = DVDD/2 (20%) Figure 18 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar, except that it contains an active pull-down circuit, thus ensuring that the AD9708 remains enabled if this input is left disconnected. The internal digital circuitry of the AD9708 is capable of operating REV. B The AD9708 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 2.7 V to 5.5 V and temperature range. This mode can be activated by applying a logic level "1" to the SLEEP pin. This digital input also contains an active pull-down circuit that ensures the AD9708 remains enabled if this input is left disconnected. The SLEEP input with active pull-down requires <40 A of drive current. The power-up and power-down characteristics of the AD9708 are dependent on the value of the compensation capacitor connected to COMP2 (Pin 23). With a nominal value of 0.1 F, the AD9708 takes less than 5 s to power down and approximately 3.25 ms to power back up. -9- AD9708 30 18 125MSPS 16 25 20 IAVDD - mA IDVDD - mA 15 10 5 2 0 2 4 6 8 12 14 IOUTFS - mA 10 16 18 20 0 0.01 0.1 RATIO (fOUT/fCLK) 5MSPS 1 0 0.01 0.1 RATIO (fOUT/fCLK) 5MSPS 1 14 12 10 8 6 4 25MSPS 2 25MSPS 50MSPS IDVDD - mA 4 50MSPS 100MSPS 6 100MSPS 8 125MSPS Figure 19. IAVDD vs. IOUTFS Figure 20. IDVDD vs. Ratio @ DVDD = 5 V Figure 21. IDVDD vs. Ratio @ DVDD = 3 V POWER DISSIPATION The power dissipation, PD, of the AD9708 is dependent on several factors, including: (1) AVDD and DVDD, the power supply voltages; (2) IOUTFS, the full-scale current output; (3) fCLOCK, the update rate; (4) and the reconstructed digital input waveform. The power dissipation is directly proportional to the analog supply current, IAVDD , and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 19, and is insensitive to fCLOCK. Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK , and digital supply DVDD. Figures 20 and 21 show IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 5 V and DVDD = 3 V, respectively. Note, how IDVDD is reduced by more than a factor of 2 when DVDD is reduced from 5 V to 3 V. FERRITE BEADS TTL/CMOS LOGIC CIRCUITS AVDD 100 F ELECT. 10-22 F TANT. 0.1 F CER. ACOM +5V OR +3V POWER SUPPLY Figure 22. Differential LC Filter for Single +5 V or +3 V Applications APPLYING THE AD9708 Power and Grounding Considerations In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection placement and routing and supply bypassing and grounding. The evaluation board for the AD9708, which uses a four layer PC board, serves as a good example for the above mentioned considerations. The evaluation board provides an illustration of the recommended printed circuit board ground, power and signal plane layouts. Proper grounding and decoupling should be a primary objective in any high speed system. The AD9708 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM as close as physically as possible. For those applications requiring a single +5 V or +3 V supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in Figure 22. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained using low ESR type electrolytic and tantalum capacitors. Maintaining low noise on power supplies and ground is critical to obtaining optimum results from the AD9708. If properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current transport, etc. In mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. All analog ground pins of the DAC, reference and other analog components, should be tied directly to the analog ground plane. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC as well as any clock signals. On the analog side, this includes the DAC output signal, reference signal and the supply feeders. The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing some "free" capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all connections be short, direct and as physically close to the package as possible in order to minimize the sharing of conduction paths between different currents. When runs exceed an inch in length, strip line techniques with proper termination resistor -10- REV. B AD9708 should be considered. The necessity and value of this resistor will be dependent upon the logic family used. For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to Analog Devices' application notes AN-280 and AN-333. DIFFERENTIAL OUTPUT CONFIGURATIONS 500 AD9708 IOUTA 22 225 225 IOUTB 21 COPT 500 25 25 AD8072 For applications requiring the optimum dynamic performance and/or a bipolar output swing, a differential output configuration is suggested. A differential output configuration may consists of either an RF transformer or a differential op amp configuration. The transformer configuration is well suited for ac coupling applications. It provides the optimum high frequency performance due to its excellent rejection of commonmode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load (i.e., assuming no source termination). The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting. Figure 23 shows the AD9708 in a typical transformer coupled output configuration. The center-tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained within the specified output compliance range of the AD9708. A differential resistor, RDIFF , may be inserted in applications in which the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination. Note that approximately half the signal power will be dissipated across RDIFF. MINI-CIRCUITS T1-1T IOUTA 22 Figure 24. DC Differential Coupling Using an Op Amp The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit is configured to provide some additional signal gain. The op amp must operate off a dual supply since its output is approximately 1.0 V. A high speed amplifier capable of preserving the differential performance of the AD9708 while meeting other system level objectives (i.e., cost, power) should be selected. The op amps differential gain, its gain setting resistor values and full-scale output swing capabilities should all be considered when optimizing this circuit. The differential circuit shown in Figure 25 provides the necessary level-shifting required in a single supply system. In this case, AVDD, which is the positive analog supply for both the AD9708 and the op amp, is also used to level-shift the differential output of the AD9762 to midsupply (i.e., AVDD/2). 500 AD9708 IOUTA 22 225 225 IOUTB 21 COPT 25 25 1k AD8072 1k AVDD Figure 25. Single-Supply DC Differential Coupled Circuit RLOAD AD9708 IOUTB 21 OPTIONAL RDIFF AD9708 EVALUATION BOARD General Description Figure 23. Differential Output Using a Transformer An op amp can also be used to perform a differential to singleended conversion as shown in Figure 24. The AD9708 is configured with two equal load resistors, RLOAD, of 25 . The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amps distortion performance by preventing the DACs high slewing output from overloading the op amp's input. The AD9708-EB is an evaluation board for the AD9708 8-bit D/A converter. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to easily and effectively evaluate the AD9708 in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9708 in various configurations. Possible output configurations include transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. The digital inputs are designed to be driven directly from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9708 with either the internal or external reference, or to exercise the power-down feature. Refer to the application note AN-420 "Using the AD9760/ AD9762/AD9764-EB Evaluation Board" for a thorough description and operating instructions for the AD9708 evaluation board. REV. B -11- DVDD B3 TP4 TP18 TP5 C4 10 F A A A DGND AVDD B4 TP19 TP6 TP7 B5 B6 AGND AVEE AVCC AD9708 B1 B2 TP3 TP2 J1 A EXTCLK 1 2 3 R15 49.9 B C3 10 F DVDD R3 16 PINDIP RES PK 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 1 U1 AVDD C7 1F A C5 10 F C6 10 F TP1 CLK JP1 DVDD R5 R7 TP8 C9 0.1 F R1 1 2 3 4 5 6 7 8 9 10 1 P1 2 3 4 5 6 7 8 9 10 AD9708 C8 0.1 F AVDD OUT 1 OUT 2 C19 C1 C2 C25 C26 C27 C28 C29 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 PINDIP RES PK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CLOCK DVDD DCOM NC AVDD COMP2 IOUTA IOUTB ACOM COMP1 FS ADJ REFIO REFLO SLEEP TP11 A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TP10 AVDD A TP9 R16 2k 1 2 JP2 3 C11 0.1 F TP14 C10 0.1 F JP4 TP13 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C30 C31 C32 C33 C34 C35 C36 1 2 3 4 5 6 7 CT1 10 9 8 7 6 5 4 3 2 TP12 1 R8 DVDD R17 49.9 1 R4 DVDD 1 10 9 8 7 6 5 4 3 2 16 15 14 13 12 11 10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Figure 26. Evaluation Board Schematic PDIN J2 A A -12- R18 1k A 10 9 8 7 6 5 4 3 2 10 9 8 7 6 5 4 3 2 A AVDD 1 R2 R6 AVCC J3 JP6A JP7B JP7A U4 JP8 R12 OPEN B 2 R10 1k A B B C20 0 A AVCC C21 0.1 F C22 1F A U7 2 AVCC OUT1 J7 3 7 REF43 J6 6 C18 0.1 F C16 1F VIN VOUT GND 6 R42 1k U6 3 C17 0.1 F A B JP3 2 1 A 4 3 R20 49.9 C12 22pF T1 AD8047 4 7 R37 49.9 A A A A 4 A JP6B A A A 3 R43 5k CW 2 R36 1k EXTREFIN J5 C14 1F AD8047 4 6 AVEE JP5 R45 1k A R14 0 5 A 1 A JP9 A 6 A A 3 R35 1k C23 0.1 F C24 1F R44 50 A 2 1 C15 0.1 F J4 R13 OPEN R9 1k B OUT2 A A R46 1k AVEE A R38 49.9 C13 22pF A A REV. B AD9708 Figure 27. Silkscreen Layer--Top Figure 28. Component Side PCB Layout (Layer 1) REV. B -13- AD9708 Figure 29. Ground Plane PCB Layout (Layer 2) Figure 30. Power Plane PCB Layout (Layer 3) -14- REV. B AD9708 Figure 31. Solder Side PCB Layout (Layer 4) Figure 32. Silkscreen Layer--Bottom REV. B -15- AD9708 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 1 14 0.4193 (10.65) 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) 0.0098 (0.25) 45 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 8 0 0.0192 (0.49) SEATING 0.0125 (0.32) PLANE 0.0138 (0.35) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.256 (6.50) 0.246 (6.25) 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) SEATING PLANE 0.0256 (0.65) BSC 8 0 0.028 (0.70) 0.020 (0.50) -16- REV. B PRINTED IN U.S.A. C2979b-1-4/99 |
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